`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:51:55 09/06/2011
// Design Name:   miter
// Module Name:   C:/Users/Tyson/Documents/Verilog Projects/CPU svn proj 3710/trunk/mitertest.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: miter
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module mitertest;

	// Outputs
   reg A, B, op;
	wire result, flags;
	
	instance alu(A,B,result, flags, op);
	
	// Instantiate the Unit Under Test (UUT)
	miter uut (
		.A(A), 
		.B(B), 
		.op(op), 
		.result(result), 
		.F(F)
	);

	initial begin
		// Initialize Inputs
	
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		integer i;
		for(i=0; i < 10; i = 1+1)begin
		   A = $random % s^16;
			B = $random % s^16;
			end
		
		$finish(0,1,2);
	end
      
endmodule

